Mercurial > unleashed > wips
changeset 20591:cb889bee4df6
10208 Add x86 features for L1TF
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Reviewed by: GergĂ Doma <domag02@gmail.com>
Approved by: Dan McDonald <danmcd@joyent.com>
| author | John Levon <john.levon@joyent.com> |
|---|---|
| date | Thu, 10 Jan 2019 17:04:14 +0000 |
| parents | 2e72e1807428 |
| children | ed6a78345203 |
| files | usr/src/uts/i86pc/os/cpuid.c usr/src/uts/intel/sys/x86_archext.h |
| diffstat | 2 files changed, 26 insertions(+), 10 deletions(-) [+] |
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--- a/usr/src/uts/i86pc/os/cpuid.c Sun Sep 16 01:43:03 2018 +0000 +++ b/usr/src/uts/i86pc/os/cpuid.c Thu Jan 10 17:04:14 2019 +0000 @@ -32,7 +32,7 @@ * Portions Copyright 2009 Advanced Micro Devices, Inc. */ /* - * Copyright 2018 Joyent, Inc. + * Copyright (c) 2019, Joyent, Inc. */ /* * Various routines to handle identification @@ -217,7 +217,9 @@ "ibrs_all", "rsba", "ssb_no", - "stibp_all" + "stibp_all", + "flush_cmd", + "l1d_vmentry_no" }; boolean_t @@ -1051,6 +1053,10 @@ add_x86_feature(featureset, X86FSET_RSBA); } + if (reg & IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY) { + add_x86_feature(featureset, + X86FSET_L1D_VM_NO); + } if (reg & IA32_ARCH_CAP_SSB_NO) { add_x86_feature(featureset, X86FSET_SSB_NO); @@ -1062,6 +1068,9 @@ if (ecp->cp_edx & CPUID_INTC_EDX_7_0_SSBD) add_x86_feature(featureset, X86FSET_SSBD); + + if (ecp->cp_edx & CPUID_INTC_EDX_7_0_FLUSH_CMD) + add_x86_feature(featureset, X86FSET_FLUSH_CMD); } } @@ -4123,7 +4132,7 @@ static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; static const struct cachetab { - uint8_t ct_code; + uint8_t ct_code; uint8_t ct_assoc; uint16_t ct_line_size; size_t ct_size;
--- a/usr/src/uts/intel/sys/x86_archext.h Sun Sep 16 01:43:03 2018 +0000 +++ b/usr/src/uts/intel/sys/x86_archext.h Thu Jan 10 17:04:14 2019 +0000 @@ -27,7 +27,7 @@ * All rights reserved. */ /* - * Copyright 2018 Joyent, Inc. + * Copyright (c) 2019, Joyent, Inc. * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> @@ -254,6 +254,7 @@ #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ +#define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ @@ -362,11 +363,12 @@ /* * Intel IA32_ARCH_CAPABILITIES MSR. */ -#define MSR_IA32_ARCH_CAPABILITIES 0x10a -#define IA32_ARCH_CAP_RDCL_NO 0x0001 -#define IA32_ARCH_CAP_IBRS_ALL 0x0002 -#define IA32_ARCH_CAP_RSBA 0x0004 -#define IA32_ARCH_CAP_SSB_NO 0x0010 +#define MSR_IA32_ARCH_CAPABILITIES 0x10a +#define IA32_ARCH_CAP_RDCL_NO 0x0001 +#define IA32_ARCH_CAP_IBRS_ALL 0x0002 +#define IA32_ARCH_CAP_RSBA 0x0004 +#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 +#define IA32_ARCH_CAP_SSB_NO 0x0010 /* * Intel Speculation related MSRs @@ -379,6 +381,9 @@ #define MSR_IA32_PRED_CMD 0x49 #define IA32_PRED_CMD_IBPB 0x01 +#define MSR_IA32_FLUSH_CMD 0x10b +#define IA32_FLUSH_CMD_L1D 0x01 + #define MCI_CTL_VALUE 0xffffffff #define MTRR_TYPE_UC 0 @@ -491,6 +496,8 @@ #define X86FSET_RSBA 78 #define X86FSET_SSB_NO 79 #define X86FSET_STIBP_ALL 80 +#define X86FSET_FLUSH_CMD 81 +#define X86FSET_L1D_VM_NO 82 /* * Intel Deep C-State invariant TSC in leaf 0x80000007. @@ -773,7 +780,7 @@ #if defined(_KERNEL) || defined(_KMEMUSER) -#define NUM_X86_FEATURES 81 +#define NUM_X86_FEATURES 83 extern uchar_t x86_featureset[]; extern void free_x86_featureset(void *featureset);